NXP Semiconductors PXN2020 - 33.4.1.4 Event Configuration Register (CTU_EVTCFGRn)

Cross Triggering Unit (CTU)
PXN20 Microcontroller Reference Manual, Rev. 1
33-6 Freescale Semiconductor
33.4.1.4 Event Configuration Register (CTU_EVTCFGRn)
Event configuration registers 0 – 31 are associated with eMIOS channels 0 – 31. Event configuration
register 32 is associated with PIT3.
Offset: CTU_BASE + 0x0020 (CTU_CVR0)
0x0024 (CTU_CVR1)
0x0028 (CTU_CVR2)
0x002C (CTU_CVR3) Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000 CV[8:0]
W
Reset0000000000000000
Table 33-5. Current Value Register (CTU_CVRn)
Table 33-6. CTU_CVRm Register Field Descriptions
Bit Description
CV[8:0] Current Value. These bits contain the current value of the counter. The counter starts counting from the start value
loaded from corresponding start value register down to 0x000 as soon as a valid input event is detected.
Offset: CTU_BASE + 0x0030–0x00B0 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TM
0
COUNT_
GROUP
0
DELAY_INDEX
CLR_
FLAG
0
CHANNEL_VALUE
W
Reset0000000000000000
Table 33-7. Event Configuration Register (CTU_EVTCFGRn)
Table 33-8. CTU_EVTCFGRn Register Field Descriptions
Bit Description
TM Trigger Mask.
0 Trigger masked.
1 Trigger enabled.