Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-28 Freescale Semiconductor
25.3.4.23 Transmit Buffer Descriptor Ring Start Register (ETDSR)
The ETDSR is written by the user. It provides a pointer to the start of the circular transmit buffer descriptor
queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made
128-bit aligned (evenly divisible by 16). Bits 30 and 31 should be written to 0 by the user. Non-zero values
in these two bit positions are ignored by the hardware.
This register is not reset and must be initialized by the user prior to operation.
Offset: FEC_BASE + 0x0180 Access: User read/write
0123456789101112131415
R
R_DES_START
W
ResetUUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
R_DES_START
00
W
ResetUUUUUUUUUUUUUUUU
Figure 25-23. Receive Descriptor Ring Start Register (ERDSR)
Table 25-25. ERDSR Field Descriptions
Field Descriptions
R_DES_START Pointer to start of receive buffer descriptor queue.
30–31 Reserved, should be cleared.
Offset: FEC_BASE + 0x0184 Access: User read/write
0123456789101112131415
R
X_DES_START
W
ResetUUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
X_DES_START
00
W
ResetUUUUUUUUUUUUUUUU
Figure 25-24. Transmit Buffer Descriptor Ring Start Register (ETDSR)
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