NXP Semiconductors PXN2020 - 26.6.4.2 FlexRay Memory Layout (MCR[FAM] = 1)

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-86 Freescale Semiconductor
Figure 26-107. Example of FlexRay Memory Layout (MCR[FAM] = 0)
26.6.4.2 FlexRay Memory Layout (MCR[FAM] = 1)
Figure 26-108 shows an example layout for the FIFO address mode MCR[FAM] = 1. The following set of
rules applies to the layout of the FlexRay memory:
• The FlexRay memory consists of two contiguous regions.
• The size of each region is maximum 64 Kbytes.
• Each region start at a 16 byte boundary.
Message Buffer Header Area
FlexRay Memory
Message Buffer Data Area
Sync Frame Table Area
Data Field OffsetFrame Header Slot Status
Data Field OffsetFrame Header Slot Status
Message Buffer Header Fields
Individual Message Buffers
Receive Shadow Buffers
Data Field OffsetFrame Header Slot Status
Data Field OffsetFrame Header Slot Status
Message Buffer Header Fields
Receive FIFO A
Data Field OffsetFrame Header Slot Status
Data Field OffsetFrame Header Slot Status
Message Buffer Header Fields
Receive FIFO B
Data Field OffsetFrame Header Slot Status
10 bytes
SYMBADR[SMBA]
System Memory