Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-23
25.3.4.15 Descriptor Individual Upper Address Register (IAUR)
The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual address
hash table used in the address recognition process to check for possible match with the DA field of receive
frames with an individual DA. This register is not reset and must be initialized by the user.
25.3.4.16 Descriptor Individual Lower Address (IALR)
The IALR register is written by the user. This register contains the lower 32 bits of the 64-bit individual
address hash table used in the address recognition process to check for possible match with the DA field
of receive frames with an individual DA. This register is not reset and must be initialized by the user.
Table 25-17. OPD Field Descriptions
Field Description
OPCODE Opcode field used in PAUSE frames.
These bits are a constant, 0x0001.
PAUSE_DUR Pause duration field used in PAUSE frames.
Offset: FEC_BASE + 0x0118 Access: User read/write
0123456789101112131415
R
IADDR1
W
ResetUUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IADDR1
W
ResetUUUUUUUUUUUUUUUU
Figure 25-16. Descriptor Individual Upper Address Register (IAUR)
Table 25-18. IAUR Field Descriptions
Field Descriptions
IADDR1 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a
unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
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