NXP Semiconductors PXN2020 - 5.4 Software-Controlled Power Management; 5.4.1 Module Disable (MDIS) Clock Gating

System Clock Description
PXN20 Microcontroller Reference Manual, Rev. 1
5-10 Freescale Semiconductor
NOTE
Unlisted peripherals such as the Flash, SIU, etc., are considered part of the
Platform and hence are not listed here.
Each divider can be changed independently of the other dividers. However, the user must ensure that the
system bus clock is always equal to or faster than the other clocks.
It should be noted that reducing clock speed for peripheral groups results in slower access times by the
device masters and may impact performance of other operations as a result of restricting bandwidth on the
respective IPS bus, or from the accessing master.
NOTE
• The ADC requires a 50% duty cycle clock. Thus, if the system clock has
been divided by its prescaler, then the ÷ 2 clock divider internal to the
ADC module must be selected (i.e., ADC MCR[ADCLKSEL] = 0).
• DMA operations are not supported for peripherals when the peripheral
clock is divided.
NOTE
• If using the PIT to trigger the CTU, do not divide the CTU peripheral
clock. SIU_SYSCLK[LPCLKDIV2] should be kept at the default
setting SIU_SYSCLK[LPCLKDIV2]=0b00.
5.4 Software-Controlled Power Management
5.4.1 Module Disable (MDIS) Clock Gating
Static clock gating is enabled by software writes to configuration bits for the modules to disable the
modules. Modules are re-enabled by software to ungate the module clocks.
The modules support software controlled clock gating where the application software can disable the
non-memory-mapped portions of the blocks by writing to module disable (MDIS) bits in registers within
the blocks. (The memory-mapped portions of the blocks are clocked by the system clock only when they
are accessed.) The Nexus port controller (NPC) can be configured to disable the MCKO signal when there
are no Nexus messages pending.
The flash array can be disabled by writing to the FDIS bit in the CRP module.
The modules that support software-controlled power management/clock gating are listed in Table 5-2
along with the registers and bits that disable each block. Default out of reset disables the
software-controlled clocks.
Table 5-1. Peripheral Sets
Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 Peripheral Set 4
All eSCI modules All FlexCAN modules ADC eMIOS
I
2
C All SPI modules CTU