Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-43
Reading/writing of a Nexus3+ register then requires two (2) passes through the data-scan (DR) path of the
JTAG state machine (see 36.6.10.8).
1. The first pass through the DR selects the Nexus3+ register to be accessed by providing an index
(see Table 36-19), and the direction (read/write). This is achieved by loading an 8-bit value into the
JTAG data register (DR). This register has the following format:
2. The second pass through the DR then shifts the data in or out of the JTAG port, LSB first.
a) During a read access, data is latched from the selected Nexus register when the JTAG state
machine passes through the CAPTURE-DR state.
b) During a write access, data is latched into the selected Nexus register when the JTAG state
machine passes through the UPDATE-DR state.
36.6.10 Nexus3+ Functional Description
36.6.10.1 Debug Status Messages
Debug Status Messages report low power mode and debug status. Debug Status Messages are enabled
when Nexus 3+ is enabled. Entering/exiting Debug Mode as well as entering a Low Power Mode triggers
a Debug Status Message, indicating the value of the most significant byte in the Development Status
register. Debug status information is sent out in the following format:
36.6.10.2 Ownership Trace
This section details the ownership trace features of the Nexus3+ module.
36.6.10.2.1 Overview
Ownership trace provides a macroscopic view, such as task flow reconstruction, when debugging software
written in a high level (or object-oriented) language. It offers the highest level of abstraction for tracking
operating system software execution. This is especially useful when the developer is not interested in
debugging at lower levels.
Nexus Register Index: Selected from values in Table 36-19
Read/Write (R/W) 0 Read
1Write
Table 36-30. Debug Status Message Format
(8 bits) (4 bits) (6 bits)
DS[31:24] Source Processor TCODE (000000)
Fixed Length = 18 bits
Nexus Register Index
(7 bits) (1 bit)
R/W
RESET Value: 0x00
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