NXP Semiconductors PXN2020 - 8.3.2.40 Masked Parallel GPIO Pin Data Output Register 4 (SIU_MPGPDO4); 8.3.2.41 Masked Parallel GPIO Pin Data Output Register 5 (SIU_MPGPDO5)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-54 Freescale Semiconductor
8.3.2.40 Masked Parallel GPIO Pin Data Output Register 4 (SIU_MPGPDO4)
The SIU_MPGPDO4 register contains the masked parallel GPIO pin data output for PE[0:15].
Writes to this register are coherent with registers SIU_GPDO64_67, SIU_GPDO68_71,
SIU_GPDO72_75, and SIU_GPDO76_79.
8.3.2.41 Masked Parallel GPIO Pin Data Output Register 5 (SIU_MPGPDO5)
The SIU_MPGPDO5 register contains the masked parallel GPIO pin data output for PF[0:15].
Writes to this register are coherent with registers SIU_GPDO80_83, SIU_GPDO84_87,
SIU_GPDO88_91, and SIU_GPDO92_95.
Offset: SIU_BASE + 0x0C8C Access: User write-only
0 1 2 3 4 5 6 7 8 9 101112131415
R0000000000000000
W PD_MASK[0:15]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PD[0:15]
Reset0000000000000000
Figure 8-47. Masked Parallel GPIO Pin Data Output Register 3 (SIU_MPGPDO3)
Offset: SIU_BASE + 0x0C90 Access: User write-only
0 1 2 3 4 5 6 7 8 9 101112131415
R0000000000000000
W PE_MASK[0:15]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PE[0:15]
Reset0000000000000000
Figure 8-48. Masked Parallel GPIO Pin Data Output Register 4 (SIU_MPGPDO4)