Peripheral Bridge (AIPS-lite)
PXN20 Microcontroller Reference Manual, Rev. 1
17-2 Freescale Semiconductor
17.1.3 Modes of Operation
The AIPS-lite has only one operating mode.
17.2 External Signal Description
The AIPS-lite has no external signals.
17.3 Memory Map and Register Description
The AIPS-lite does not contain any user-programmable registers.
17.4 Functional Description
The AIPS-lite serves as an interface between an AHB 2.v6 system bus and the peripheral interface bus. It
functions as a protocol translator.
Accesses that fall within the address space of the AIPS-lite are decoded to provide individual module
selects for peripheral devices on the peripheral bus interface.
See the peripherals section of Table 2-1 for a description of which peripherals are allocated to which
16 KB memory space in the AIPS-lite address map.
17.4.1 Read Cycles
Two-clock read accesses are possible with the AIPS-Lite when the reference size is 32 bits or smaller. This
module does not support any type of misaligned read accesses crossing a 32-bit boundary.
17.4.2 Write Cycles
Two-clock write accesses are possible with the AIPS-Lite when the reference size is 32 bits or smaller.
This module does not support any type of misaligned write accesses crossing a 32-bit boundary.
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