NXP Semiconductors PXN2020 - 26.5.2.14 Protocol Interrupt Enable Register 1 (PIER1)

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-27
26.5.2.14 Protocol Interrupt Enable Register 1 (PIER1)
This register defines whether or not the individual interrupt flags defined in Protocol Interrupt Flag
Register 1 (PIFR1) can generate a protocol interrupt request.
LTXA_IE pLatestTx Violation on Channel A Interrupt Enable — This bit controls LTXA_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
TBVB_IE Transmission across boundary on channel B Interrupt Enable — This bit controls TBVB_IF interrupt request
generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
TBVA_IE Transmission across boundary on channel A Interrupt Enable — This bit controls TBVA_IF interrupt request
generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
TI2_IE Timer 2 Expired Interrupt Enable — This bit controls TI1_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
TI1_IE Timer 1 Expired Interrupt Enable — This bit controls TI1_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
CYS_IE Cycle Start Interrupt Enable — This bit controls CYC_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Base + 0x001E Write: Anytime
0123456789101112131415
R
EMC
_IE
IPC
_IE
PECF
_IE
PSC
_IE
SSI3
_IE
SSI2
_IE
SSI1
_IE
SSI0
_IE
00
EVT
_IE
ODT
_IE
0000
W
Reset0000000000000000
Figure 26-14. Protocol Interrupt Enable Register 1 (PIER1)
Table 26-20. PIER1 Field Descriptions
Field Description
EMC_IE Error Mode Changed Interrupt Enable — This bit controls EMC_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
IPC_IE Illegal Protocol Control Command Interrupt Enable — This bit controls IPC_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Table 26-19. PIER0 Field Descriptions (continued)
Field Description