NXP Semiconductors PXN2020 - 27.4 Functional Description

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
27-26 Freescale Semiconductor
27.4 Functional Description
The MLB Device peripheral is divided into six main components, as illustrated in Figure 27-1.
• MLB Core. Implements the physical layer of the MLB interface. This physical layer performs
serial-to-parallel and parallel-to-serial data transformations and MLB frame synchronization.
• Clock and Reset Control
• MLB Link Logic. Implements the link layer functionality of the MLB interface, including:
— Checking of synchronous, asynchronous, control, and isochronous channel protocol
— Handling of both RX and TX initiated breaks
— Generating RX responses to the MLB Core
— Generating TX commands for the MLB Core
— Processing of and responding to the system channel commands
— Detection of MLB bus lock/unlock
— Recognition and pipe-lining of logical ChannelAddresses
• MLB Configuration Logic. Implements the memory space for the Configuration Control Registers
and Channel Configuration Registers. These configuration and control registers are used to define
Table 27-22. Local Channel n Buffer Configuration Register Field Descriptions
Field Description
BD[8:0] Buffer Depth. This field defines the depth of the local channel buffer in the local buffer RAM in increments of 4
quadlets. At reset, the LCBCHn[BD[8:0]] field is loaded with 0x01F, or 128 quadlets.
0x000 – Depth = 4 quadlets.
0x001 – Depth = 8 quadlets.
0x002 – Depth = 12 quadlets.
...
0x1FF – Depth = 2048 quadlets.
Value 0x01F (decimal 31) equates to 128 quadlets.
The default buffer depth for all channels is 128 quadlets (0x01F).
SA[8:0] Buffer Start Address. This field defines the starting address of the channel buffer space in the local buffer RAM in
increments of 4 quadlets. At reset, the LCBCRn[SA[9:0]] field is loaded with the channel number multiplied by 32 (or
channel number multiplied by 128 quadlets).
0x000 – RAM Start Address offset = 0 quadlets.
0x001 – RAM Start Address offset = 4 quadlets.
0x002 – RAM Start Address offset = 8 quadlets.
...
0x1FFh – RAM Start Address offset = 2044 quadlets.
General: Channel n offset = Channel (n – 1)offset + BD(Channel (n – 1)).
Channel 0 = 0 offset.
Channel 1 = Channel 0 + BD(16quadlets) = 16quadlets offset.
Channel 2 = Channel 1 (16quadlets) + BD(16 quadlets) = 32 quadlets offset.
Channel 3 = Channel 2 (32 quadlets) + BD(144 quadlets) = 176 quadlets offset.
Channel 4 = Channel 3 (176 quadlets) + BD(144 quadlets) = 320 quadlets offset.