NXP Semiconductors PXN2020 - 31.4.6.7 LIN Protocol Engine Reset; 31.4.7 Interrupts; 31.4.7.1 Interrupt Flags and Enables

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-51
• Reception of a LIN 1.x wakeup character (0x80, 0x00 or oxC0)
• Reception of a LIN 2.0 wakeup character (low pulse of 250 ms to 5 ms).
To detect LIN 2.0 wakeup characters, the baud rate must to be set to 32 kbaud down to 1.6 kbaud.
NOTE
If the eSCI module is transmitting a LIN frame and the application sets and
clears the LIN Finite State Machine Resync bit in the LIN Control Register
1 (eSCI_LCR1[LRES]) to abort the transmission, the LIN Wakeup Receive
Flag in the LIN StatusRegister may be set (LWAKE=1). To avoid this, if the
application has triggered LIN Protocol Engine Reset via the
eSCI_LCR1[LRES], it should wait for the duration of a frame and clear the
eSCI_IFSR2[LWAKE] flag before waiting for a wakeup.
NOTE
If the eSCI module is in LIN mode and is transmitting a LIN frame, and the
application sets and subsequently clears the LIN reset bit (LRES) in the LIN
Control register 1 (ESCI_LCR1), the next LIN frame transmission might
incorrectly signal the occurrence of bit errors (ESCI_IFSR1[BERR]) and
frame error (ESCI_IFSR1[FE]), and the transmitted frame might be
incorrect.
31.4.6.7 LIN Protocol Engine Reset
The LIN protocol engine is reset when the LRES bit in the eSCI LIN Control Register 1 (eSCI_LCR1) is
set to 1. In this case, the LIN protocol engine will no longer initiate new transmissions or receptions.
However, ongoing byte transmission or reception is not halted.
In order to start the LIN Protocol Engine with idle transmitter and receiver processes, the LRES bit should
be asserted for the duration of at least one bit.
31.4.7 Interrupts
This section describes the interrupt sources and interrupt request generation.
31.4.7.1 Interrupt Flags and Enables
All interrupt sources, interrupt flags, and interrupt enable bits are listed in Table 31-33. This table indicates
the operational modes, where the interrupt flags can be set by the eSCI module.
Table 31-33. eSCI Interrupt Flags and Interrupt Enable Bits
Interrupt Source Interrupt Flag Interrupt Enable Interrupt Enable Bit
Transmitter SCI eSCI_IFSR1[TDRE] eSCI_CR1[TIE]
Transmitter SCI, LIN eSCI_IFSR1[TC] eSCI_CR1[TCIE]
Receiver SCI eSCI_IFSR1[RDRF] eSCI_CR1[RIE]
Receiver SCI eSCI_IFSR1[IDLE] eSCI_CR1[ILIE]