NXP Semiconductors PXN2020 - 12.3.2.9 Platform Flash Access Protection Register (PFAPR)

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-20 Freescale Semiconductor
12.3.2.9 Platform Flash Access Protection Register (PFAPR)
PFLIM[1:0] PFLASH Prefetch Limit. Controls the prefetch algorithm used by the PFLASH prefetch controller. This field
defines a limit on the maximum number of sequential prefetches that are attempted between buffer misses. In all
situations when enabled, only a single prefetch is initiated on each buffer miss or hit. This field is cleared by
hardware reset.
00 No prefetching or buffering is performed.
01 The referenced line is prefetched on a buffer miss, i.e., prefetch on miss.
1x the referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if
not already present), i.e., prefetch on miss or hit.
BFEN PFLASH Line Read Buffers Enable. Enables or disables line read buffer hits. It is also used to invalidate the
buffers. This bit is cleared by hardware reset.
0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.
1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers
are successfully filled.
Offset: FLASH_REGS_BASE + 0x0024 Access: User read/write
0123456789101112131415
R
M7AP M6AP M5AP M4AP M3AP M2AP M1AP M0AP
W
Reset0000000011111111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SHSACC
0000
SHDACC
0000
W
Reset1111000000000000
Figure 12-11. PFlash Access Protection Register (PFAPR)
Table 12-12. PFlash Access Protection Register (PFAPR) Field Descriptions
Field Description
M7AP
...
M0AP
Master X Access Protection. These fields are used to control whether read and write accesses to the flash are
allowed based on the master ID of a requesting master.
00 No accesses may be performed by this master.
01 Only read accesses may be performed by this master.
10 Only write accesses may be performed by this master.
11 Both read and write accesses may be performed by this master.
Table 12-11. PFCRP0 and PFCRP1 Field Descriptions (continued)
Field Description
Bit
Bus Master
Bit
Bus Master
M0AP 0 — Z6 Core M4AP 4 — FEC
M1AP 1 — Z0 Core M5AP 5 — MLB
M2AP 2 — eDMA M6AP 6 — FlexRay
M3AP 3 — reserved M7AP 7 — reserved