Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 12-19
APC[2:0] Address Pipelining Control. Used to control the number of cycles between pipelined access requests.
This field must be set to a value corresponding to the operating frequency of the PFLASH. The settings are
documented in the PXN20 Microcontroller Data Sheet. Higher operating frequencies require non-zero settings
for this field for proper flash operation. This field is set to 0b111 by hardware reset.
000 Accesses may be pipelined back-to-back.
001 Access requests require one additional hold cycle.
010 Access requests require two additional hold cycles.
...
110 Access requests require six additional hold cycles.
111 No address pipelining.
Note: The settings for APC and RWSC should be the same.
WWSC[1:0] Write Wait State Control. Used to control the number of wait states to be added to the best case flash array
access time for writes. This field must be set to a value corresponding to the operating frequency of the PFLASH.
Higher operating frequencies require non-zero settings for this field for proper flash operation. This field is set to
0b11 by hardware reset.
00 No additional wait-states are added.
01 One additional wait-state is added.
10 Two additional wait-states are added.
11 Three additional wait-states are added.
RWSC[2:0] Read Wait State Control. Used to control the number of wait states to be added to the best case flash array
access time for reads. This field must be set to a value corresponding to the operating frequency of the PFLASH
and the actual read access time of the PFLASH. This field is set to 0b111 by hardware reset.
000 No additional wait states are added.
001 One additional wait state is added.
...
111 Seven additional wait states are added.
Note: The settings for APC and RWSC should be the same.
DPFEN Data Prefetch Enable. Enables or disables prefetching initiated by a data read access. This field is cleared by
hardware reset.
0 No prefetching is triggered by a data read access.
1 Prefetching may be triggered by any data read access.
IPFEN Instruction Prefetch Enable. Enables or disables prefetching initiated by an instruction read access. This field is
cleared by hardware reset.
0 No prefetching is triggered by an instruction read access.
1 Prefetching may be triggered by any instruction read access.
Table 12-11. PFCRP0 and PFCRP1 Field Descriptions (continued)
Field Description
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