Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-14 Freescale Semiconductor
Depending on the channel configuration it may have an internal counter or not. It means that if at least one
mode that requires the counter is implemented, then the counter is present, otherwise it is absent.
28.3.2.8 eMIOS200 Control Register (EMIOS_CCR[n])
The control register gathers bits reflecting the status of the unified channel input/output signals and the
overflow condition of the internal counter, as well as several read/write control bits.
Offset: UC[n] base address + 0x000C Access: User read/write
012 3456789101112131415
R
FREN ODIS ODISSL UCPRE
UC
PREN
DMA
0
IF FCK FEN
0
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0
FORC
MA
FORC
MB
0
BSL
ED
SEL
ED
POL
MODE[0:6]
W
Reset0000000000000000
Figure 28-10. eMIOS200 Control Register (EMIOS_CCR[n])
Table 28-10. EMIOS_CCR[n] Field Descriptions
Field Description
FREN Freeze Enable Bit. The FREN bit, if set and validated by FRZ bit in EMIOS_MCR register, freezes all registers’
values when in debug mode, allowing the MCU to perform debug functions.
0 Normal operation.
1 Freeze unified channel registers’ values.
ODIS Output Disable Bit. The ODIS bit allows disabling the output pin when running any of the output modes with
the exception of GPIO mode.
0 The output pin operates normally.
1 If the selected output disable input signal is asserted, the output pin goes to EDPOL for OPWFMB and
OPWMB modes and to the complement of EDPOL for other modes, but the unified channel continues to
operate normally, i.e., it continues to produce FLAG and matches. When the selected output disable input
signal is negated, the output pin operates normally.
ODISSL Output Disable Select Bits. The ODISSL bits select one of the four output disable input signals.
ODISSL Input Signal
00 Output disable input 0
01 Output disable input 1
10 Output disable input 2
11 Output disable input 3
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