NXP Semiconductors PXN2020 - 33.4.1.2 Start Value Register (CTU_SVRn); 33.4.1.3 Current Value Register (CTU_CVRm)

Cross Triggering Unit (CTU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 33-5
33.4.1.2 Start Value Register (CTU_SVRn)
The CTU_SVRn registers contain the start values to be loaded into the CTU_CVRm registers.
33.4.1.3 Current Value Register (CTU_CVRm)
The CTU_CVRm registers contain the current count value.
PRESC_
CONF
Prescaler Configuration.
The counter clock is derived from the system clock by dividing it by 2
0
to 2
10
depending on the prescaler configuration
bits. The clock division coding is as follows:
0000 Clock divided by 1 (no division).
0001 Clock divided by 2.
0010 Clock divided by 4.
0011 Clock divided by 8.
0100 Clock divided by 16.
0101 Clock divided by 32.
0110 Clock divided by 64.
0111 Clock divided by 128.
1000 Clock divided by 256.
1001 Clock divided by 512.
1010 Clock divided by 1024.
1011 – 1111 Clock divided by 1(no division).
Offset: CTU_BASE + 0x0004 (CTU_SVR1)
0x0008 (CTU_SVR2)
0x000C(CTU_SVR3)
0x0010 (CTU_SVR4)
0x0014 (CTU_SVR5)
0x0018 (CTU_SVR6)
0x001C (CTU_SVR7)
Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000
SV[8:0]
W
Reset0000000000000000
Table 33-3. Start Value Register (CTU_SVRn)
Table 33-4. CTU_SVRn Register Field Descriptions
Bit Description
SV[8:0] Start Value. These bits store the start value of the counting to be loaded into the current value register whenever an
event mapped to this start value register is serviced.
Table 33-2. CTU_CSR Register Field Descriptions (continued)
Bit Description