NXP Semiconductors PXN2020 - 30.1.1 Block Diagram; 30.1.2 Features

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-2 Freescale Semiconductor
30.1.1 Block Diagram
Figure 30-2 is a simplified block diagram of the DSPI that illustrates the functionality and interdependence
of major blocks.
Figure 30-2. DSPI Block Diagram
30.1.2 Features
The DSPI supports these SPI features:
• Full-duplex, three-wire synchronous transfers
• Master and slave mode
• Buffered transmit operation using the TX FIFO with depth of 4 entries
• Buffered receive operation using the RX FIFO with depth of 4 entries
• TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
• Visibility into TX and RX FIFOs for ease of debugging
• Programmable transfer attributes on a per-frame basis:
CMD
DMA and interrupt control
TX FIFO RX FIFO
TX data RX data
16
16
Shift register
SOUT
SPI
SPI and DSI baud rate,
delay and transfer
control
CSI
priority
logic
TXSS
DSI
32
Internal
32
SIN
SCK
PCS[0]/SS
PCS[4:1]
PCS[5]/PCSS
INTCeDMA
4
16
16
16
16
16
32
32
16
16
Parallel Inputs
Internal
Parallel Outputs