NXP Semiconductors PXN2020 - 30.3.2.2 DSPI Transfer Count Register (DSPI_TCR)

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-9
30.3.2.2 DSPI Transfer Count Register (DSPI_TCR)
The DSPI_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter
is intended to assist in queue management.
NOTE
The user must not write to the DSPI_TCR while the DSPI is running.
DIS_RXF Disable Receive FIFO. The DIS_RXF bit provides a mechanism to disable the RX FIFO. When the RX FIFO
is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI. See Section 30.4.3.3,
FIFO Disable Operation, for details.
0 RX FIFO is enabled.
1 RX FIFO is disabled.
CLR_TXF Clear TX FIFO. CLR_TXF is used to flush the TX FIFO. Writing a ‘1’ to CLR_TXF clears the TX FIFO Counter.
The CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO Counter.
1 Clear the TX FIFO Counter.
CLR_RXF Clear RX FIFO. CLR_RXF is used to flush the RX FIFO. Writing a ‘1’ to CLR_RXF clears the RX Counter. The
CLR_RXF bit is always read as zero.
0 Do not clear the RX FIFO Counter.
1 Clear the RX FIFO Counter.
SMPL_PT SMPL_PT — Sample Point. SMPL_PT allows the host software to select when the DSPI Master samples SIN
in Modified Transfer Format. Figure 30-31 shows where the master can sample the SIN pin. The table below
lists the various delayed sample points.
HALT Halt. The HALT bit provides a mechanism by software to start and stop DSPI transfers. See Section 30.4.2,
Start and Stop of DSPI Transfers, for details on the operation of this bit.
0 Start transfers.
1 Stop transfers.
Table 30-3. DSPI_MCR Field Descriptions (continued)
Field Description
SMPL_PT
Number of system clock cycles between
odd-numbered edge of SCKn and sampling of SINn.
00 0
01 1
10 2
11 Reserved