Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-8 Freescale Semiconductor
DCONF DSPI Configuration. The DCONF field selects between the three different configurations of the DSPI. The
values below list the DCONF values for the various configurations.
FRZ Freeze. The FRZ bit enables the DSPI transfers to be stopped on the next frame boundary when the device
enters Debug Mode.
0 Do not halt serial transfers.1Halt serial transfers.
MTFE Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used. See
Section 30.4.8.4, Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1), for more information.
0 Modified SPI transfer format disabled.
1 Modified SPI transfer format enabled.
PCSSE Peripheral Chip Select Strobe Enable. The PCSSE bit enables the PCS[5]/PCSS
to operate as an PCS Strobe
output signal. See Section 30.4.7.5, Peripheral Chip Select Strobe Enable (PCSS), for more information.
0 PCS[5]/PCSS
is used as the Peripheral Chip Select[5] signal.
1 PCS[5]/PCSS is used as an active-low PCS Strobe signal.
ROOE Receive FIFO Overflow Overwrite Enable. The ROOE bit enables an RX FIFO overflow condition to either
ignore the incoming serial data or to overwrite existing data. If the RX FIFO is full and new data is received,
the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. If the
ROOE bit is asserted, the incoming data is shifted in to the shift register. If the ROOE bit is negated, the
incoming data is ignored. See Section 30.4.12.6, Receive FIFO Overflow Interrupt Request, for more
information.
0 Incoming data is ignored.
1 Incoming data is shifted in to the shift register.
PCSISn Peripheral Chip Select Inactive State. The PCSIS bit determines the inactive state of the PCS[x] signal.
0 The inactive state of PCS[x] is low.
1 The inactive state of PCS[x] is high.
MDIS Module Disable. The MDIS bit allows the clock to be stopped to the non-memory mapped logic in the DSPI
effectively putting the DSPI in a software controlled power-saving state. See Section 30.4.13, Power Saving
Features, for more information. The reset value of the MDIS bit is parameterized, with a default reset value of
‘1’.
0 Enable DSPI clocks.
1 Allow external logic to disable DSPI clocks.
DIS_TXF Disable Transmit FIFO. The DIS_TXF bit provides a mechanism to disable the TX FIFO. When the TX FIFO
is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI. See Section 30.4.3.3,
FIFO Disable Operation, for details.
0 TX FIFO is enabled.
1 TX FIFO is disabled.
Table 30-3. DSPI_MCR Field Descriptions (continued)
Field Description
DCONF DSPI Configuration
00 SPI
01 DSI
10 CSI
11 Reserved
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