Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-25
25.3.4.18 Descriptor Group Lower Address (GALR)
The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash table
used in the address recognition process for receive frames with a multicast address. This register must be
initialized by the user.
25.3.4.19 FIFO Transmit FIFO Watermark Register (TFWR)
The TFWR is a 32-bit read/write register with one 2-bit field programmed by the user to control the
amount of data required in the transmit FIFO before transmission of a frame can begin. This allows the
user to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11) due
to contention for the system bus. Setting the watermark to a high value minimizes the risk of transmit FIFO
underrun due to contention for the system bus. The byte counts associated with the TFWR field may need
to be modified to match a given system requirement (worst case bus access latency by the transmit data
DMA channel).
Table 25-20. GAUR Field Descriptions
Field Description
GADDR1 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of
GADDR1 contains hash index bit 32.
Offset: FEC_BASE + 0x0124 Access: User read/write
0123456789101112131415
R
GADDR2
W
ResetUUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GADDR2
W
ResetUUUUUUUUUUUUUUUU
Figure 25-19. Descriptor Group Lower Address Register (GALR)
Table 25-21. GALR Field Descriptions
Field Description
GADDR2 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of
GADDR2 contains hash index bit 0.
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