Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-27
25.3.4.21 FIFO Receive Start Register (FRSR)
The FRSR is a 32-bit register with one 8-bit field programmed by the user to indicate the starting address
of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit
FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed
into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive.
The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the default
value.
25.3.4.22 Receive Descriptor Ring Start (ERDSR)
The ERDSR is written by the user. It provides a pointer to the start of the circular receive buffer descriptor
queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made
128-bit aligned (evenly divisible by 16).
This register is not reset and must be initialized by the user prior to operation.
Table 25-23. FRBR Field Descriptions
Field Descriptions
0–21 Reserved, read as 0 (except bit 21, which is read as 1).
R_BOUND Read-only. Highest valid FIFO RAM address.
30–31 Reserved, should be cleared.
Offset: FEC_BASE + 0x0150 Access: User read/write
0123456789101112131415
R0 000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000 R_FSTART 00
W
Reset0000010100000000
Figure 25-22. FIFO Receive Start Register (FRSR)
Table 25-24. FRSR Field Descriptions
Field Descriptions
0–21 Reserved, read as 0 (except bit 21, which is read as 1).
R_FSTART Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs.
30–31 Reserved, read as 0.
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