NXP Semiconductors PXN2020 - 27.3.2 Register Descriptions; 27.3.2.1 Device Control Configuration Register (DCCR)

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Media Local Bus (MLB)

PXN20 Microcontroller Reference Manual, Rev. 1

27-8 Freescale Semiconductor

27.3.2 Register Descriptions

27.3.2.1 Device Control Configuration Register (DCCR)

The Device Control Configuration Register (DCCR) is used to control basic features of the MLB device,

such as clock rate, lock status, enable, and reset behavior.

0x0140–0x027F Reserved

0x0280 LCBCR0—Local Channel 0 Buffer Configuration Register R/W 0x0803_E000 27.3.2.15/27-24

0x0284 LCBCR1—Local Channel 1 Buffer Configuration Register R/W 0x0803_E020 27.3.2.15/27-24

0x0288 LCBCR2—Local Channel 2 Buffer Configuration Register R/W 0x0803_E040 27.3.2.15/27-24

0x028C LCBCR3—Local Channel 3 Buffer Configuration Register R/W 0x0803_E060 27.3.2.15/27-24

0x0290 LCBCR4—Local Channel 4 Buffer Configuration Register R/W 0x0803_E080 27.3.2.15/27-24

0x0294 LCBCR5—Local Channel 5 Buffer Configuration Register R/W 0x0803_E0A0 27.3.2.15/27-24

0x0298 LCBCR6—Local Channel 6 Buffer Configuration Register R/W 0x0803_E0C0 27.3.2.15/27-24

0x029C LCBCR7—Local Channel 7 Buffer Configuration Register R/W 0x0803_E0E0 27.3.2.15/27-24

0x02A0 LCBCR8—Local Channel 8 Buffer Configuration Register R/W 0x0803_E100 27.3.2.15/27-24

0x02A4 LCBCR9—Local Channel 9 Buffer Configuration Register R/W 0x0803_E120 27.3.2.15/27-24

0x02A8 LCBCR10—Local Channel 10 Buffer Configuration Register R/W 0x0803_E140 27.3.2.15/27-24

0x02AC LCBCR11—Local Channel 11 Buffer Configuration Register R/W 0x0803_E160 27.3.2.15/27-24

0x02B0 LCBCR12—Local Channel 12 Buffer Configuration Register R/W 0x0803_E180 27.3.2.15/27-24

0x02B4 LCBCR13—Local Channel 13 Buffer Configuration Register R/W 0x0803_E1A0 27.3.2.15/27-24

0x02B8 LCBCR14—Local Channel 14 Buffer Configuration Register R/W 0x0803_E1C0 27.3.2.15/27-24

0x02BC LCBCR15—Local Channel 15 Buffer Configuration Register R/W 0x0803_E1E0 27.3.2.15/27-24

0x02C0–0x3FFF Reserved

Note that R/W registers may contain some read-only or write-only bits.

Table 27-7. MLB Memory Map (continued)

Offset from

MLB_BASE

(

0xC3F8_4000)

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