NXP Semiconductors PXN2020 - 36.6.8.7 Data Trace Control Register (DTC)

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-40 Freescale Semiconductor
NOTE
The WT bits can control program/data trace only if the TM bits in the
development control register 1 (DC1) have not already been set to enable
program and data trace, respectively.
36.6.8.7 Data Trace Control Register (DTC)
The data trace control register controls whether DTM messages are restricted to reads, writes, or both for
a user programmable address range. Two data trace channels are controlled by the DTC for the Nexus3
module. Each channel can also be programmed to trace data accesses or instruction accesses.
Table 36-28 details the data trace control register fields.
DTS Data Trace Start Control.
000 Trigger disabled.
001 Use watchpoint #0 (IAC1 from Nexus1).
010 Use watchpoint #1 (IAC2 from Nexus1).
011 Use watchpoint #2 (IAC3 from Nexus1).
100 Use watchpoint #3 (IAC4 from Nexus1).
101 Use watchpoint #4 (DAC1 from Nexus1).
110 Use watchpoint #5 (DAC2 from Nexus1).
111 Use watchpoint #6 or #7 (DCNT1 or DCNT2 from Nexus1).
DTE Data Trace End Control.
000 Trigger disabled.
001 Use watchpoint #0 (IAC1 from Nexus1).
010 Use watchpoint #1 (IAC2 from Nexus1).
011 Use watchpoint #2 (IAC3 from Nexus1).
100 Use watchpoint #3 (IAC4 from Nexus1).
101 Use watchpoint #4 (DAC1 from Nexus1).
110 Use watchpoint #5 (DAC2 from Nexus1).
111 Use watchpoint #6 or #7 (DCNT1 or DCNT2 from Nexus1).
Nexus Reg: 0xD Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RWT1 RWT2
000000000000
W
Reset0000000000000000
1514131211109876543210
R00000000
RC1 RC2
00
DI1 DI2
00
W
Reset0000000000000000
Figure 36-21. Data Trace Control Register (DTC)
Table 36-27. WT Field Descriptions (continued)
Field Description