NXP Semiconductors PXN2020 - 10.5.4 Order of Execution

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-41
10.5.4 Order of Execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors
associated with each of their peripheral or software settable interrupt requests. However, if multiple
peripheral or software settable interrupt requests are asserted, more than one has the highest priority, and
that priority is high enough to cause preemption, the INTC selects the one with the lowest unique vector
regardless of the order in time that they asserted. However, the ability to meet deadlines with this
scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software
settable interrupt requests asserted.
The example in Table 10-13 shows the order of execution of both ISRs with different priorities and the
same priority.
Table 10-13. Order of ISR Execution Example
Step# Step Description
Code Executing at End of Step
PRI in
INTC_CPR
at End of
Step
RTOS ISR108
1
1
ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software settable interrupt requests.
ISR208 ISR308 ISR408
Interrupt
Exception
Handler
1 RTOS at priority 0 is executing. X 0
2 Peripheral interrupt request 100 at priority 1
asserts. Interrupt taken.
X1
3 Peripheral interrupt request 400 at priority 4 is
asserts. Interrupt taken.
X4
4 Peripheral interrupt request 300 at priority 3 is
asserts.
X4
5 Peripheral interrupt request 200 at priority 3 is
asserts.
X4
6 ISR408 completes. Interrupt exception
handler writes to INTC_EOIR_PRCn.
X1
7 Interrupt taken. ISR208 starts to execute,
even though peripheral interrupt request 300
asserted first.
X3
8 ISR208 completes. Interrupt exception
handler writes to INTC_EOIR_PRCn.
X1
9 Interrupt taken. ISR308 starts to execute. X 3
10 ISR308 completes. Interrupt exception
handler writes to INTC_EOIR_PRCn.
X1
11 ISR108 completes. Interrupt exception
handler writes to INTC_EOIR_PRCn.
X0
12 RTOS continues execution. X 0