NXP Semiconductors PXN2020 - 22.3.2.4 Timer n Control Register (TCTRLn)

Periodic Interrupt Timer (PIT)
PXN20 Microcontroller Reference Manual, Rev. 1
22-6 Freescale Semiconductor
22.3.2.4 Timer n Control Register (TCTRLn)
These registers contain the control bits for each timer.
Offset: Channel_base + 0x0004
LDVAL1 = 0x0104
LDVAL2 = 0x0114
LDVAL3 = 0x0124
LDVAL4 = 0x0134
LDVAL5 = 0x0144
LDVAL6 = 0x0154
LDVAL7 = 0x0164
LDVAL8 = 0x0174
Access: User read/write
0123456789101112131415
R
TVL31 TVL30 TVL29 TVL28 TVL27 TVL26 TVL25 TVL24 TVL23 TVL22 TVL21 TVL20 TVL19 TVL18 TVL17 TVL16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TVL15 TVL14 TVL13 TVL12 TVL11 TVL10 TVL9 TVL8 TVL7 TVL6 TVL5 TVL4 TVL3 TVL2 TVL1 TVL0
W
Reset0000000000000000
Figure 22-4. Timer n Current Value Register (CVALn)
Table 22-5. CVALn Field Descriptions
Field Description
TVLn Current Timer Value. These bits represent the current timer value. Note that the timer uses a down counter.
Note: The timer values are frozen in Debug mode if the FRZ bit is set in the PIT Module Control Register (see
Figure 22-2).
Offset: Channel_base + 0x0008
LDVAL1 = 0x0108
LDVAL2 = 0x0118
LDVAL3 = 0x0128
LDVAL4 = 0x0138
LDVAL5 = 0x0148
LDVAL6 = 0x0158
LDVAL7 = 0x0168
LDVAL8 = 0x0178
Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000000000
TIE TEN
W
Reset0000000000000000
Figure 22-5. Timer n Control Register (TCTRLn)