Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-30 Freescale Semiconductor
25.4.1 Initialization Sequence
This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC,
and what locations the user must initialize prior to enabling the FEC.
25.4.1.1 Hardware Controlled Initialization
In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware reset
deasserts output signals and resets general configuration bits.
Other registers reset when the ECR[ETHER_EN] bit is cleared. ECR[ETHER_EN] is deasserted by a hard
reset or may be deasserted by software to halt operation. By deasserting ECR[ETHER_EN], the
configuration control registers such as the TCR and RCR are not reset, but the entire data path is reset.
25.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN])
The user needs to initialize portions of the FEC prior to setting the ECR[ETHER_EN] bit. The exact values
depend on the particular application. The sequence is not important.
Ethernet MAC registers requiring initialization are defined in Table 25-29.
FEC FIFO/DMA registers that require initialization are defined in Table 25-30.
Table 25-28. ECR[ETHER_EN] De-Assertion Effect on FEC
Register/Machine Reset Value
XMIT block Transmission is aborted (bad CRC appended)
RECV block Receive activity is aborted
DMA block All DMA activity is terminated
RDAR Cleared
TDAR Cleared
Descriptor Controller block Halt operation
Table 25-29. User Initialization (Before ECR[ETHER_EN])
Description
Initialize EIMR
Clear EIR (write 0xFFFF_FFFF)
TFWR (optional)
IALR / IAUR
GAUR / GALR
PALR / PAUR (only needed for full duplex flow control)
OPD (only needed for full duplex flow control)
RCR
TCR
MSCR (optional)
Clear MIB_RAM (locations Base + 0x0200 – 0x02FC)
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