NXP Semiconductors PXN2020 - 21.3.2.3 STM Channel Control Register (STM_CCRn); 21.3.2.4 STM Channel Interrupt Register (STM_CIRn)

System Timer Module (STM)
PXN20 Microcontroller Reference Manual, Rev. 1
21-4 Freescale Semiconductor
21.3.2.3 STM Channel Control Register (STM_CCRn)
The STM Channel Control Register (STM_CCRn) is used to enable and service channel n of the timer.
21.3.2.4 STM Channel Interrupt Register (STM_CIRn)
The STM Channel Interrupt Register (STM_CIRn) is used to enable and service channel n of the timer.
Offset STM_CCR0: STM_BASE + 0x0010
STM_CCR1: STM_BASE + 0x0020
STM_CCR2: STM_BASE + 0x0030
STM_CCR3: STM_BASE + 0x0040
Access: User read/write
0123456789101112131415
R 0 0 0 0 0 00000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 000000000 00000
CEN
W
Reset0000000000000000
Figure 21-3. STM Channel Status and Control Register (STM_CCRn)
Table 21-4. STM_CCRn Field Descriptions
Field Description
CEN Channel Enable.
0 The channel is disabled.
1 The channel is enabled.
Offset: STM_CIR0: STM_BASE + 0x0014
STM_CIR1: STM_BASE + 0x0024
STM_CIR2: STM_BASE + 0x0034
STM_CIR3: STM_BASE + 0x0044
Access: User read/write
0123456789101112131415
R 0 0 0 0 0 00000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 000000000 00000
CIF
W
Reset0000000000000000
Figure 21-4. STM Channel Interrupt Register (STM_CIRn)