Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
18-2 Freescale Semiconductor
Figure 18-1. MPU Connections to AXBS-lite
Figure 18-2.
18.1.2 Features
The MPU has these major features:
Support for 16 memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to
4GB
— MPU is invalid at reset, thus no access restrictions are enforced
Table 18-1. Master Assignments and Master IDs
AXBS Port AXBS Module Master ID
M0 Z6 Core 0
Z6 Nexus 8
M1 eDMA 2
M2 Off Platform (MLB) 5
M3 FEC 4
M6 Off Platform (FlexRay) 6
M7 Z0 Core 1
AXBS
512K SRAM
AIPS_A
Flash Port 1
MLB
FEC
e200z6
e200z0
FlexRay
Flash Port 0 (e200z6)
MPU
Master ID 1
Master ID 0 (8 for Nexus)
Master ID 2
Master ID 5
Master ID 6
Master ID 4
m7
m1
m3
m0
m6
m2
MPU0
s3
s0
s1
s2
s6
s7
80K SRAM
MPU1 MPU2 MPU3
AIPS_B
(Master ID 3, 7 not used)
ports
Master Slave
Note: AXBS Master port numbers
do not correspond to Master ID numbers.
eDMA
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