FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-16 Freescale Semiconductor
NOTE
The system memory base address must be set before the controller is
enabled.
The system memory base address registers define the base address of the FlexRay memory within the
system memory. The base address is used by the BMIF to calculate the physical memory address for
system memory accesses.
26.5.2.6 Strobe Signal Control Register (STBSCR)
This register is used to assign the individual protocol timing related strobe signals given in Table 26-12 to
the external strobe ports. Each strobe signal can be assigned to at most one strobe port. Each write access
to registers overwrites the previously written ENB and STBPSEL values for the signal indicated by SEL.
If more than one strobe signal is assigned to one strobe port, the current values of the strobe signals are
combined with a binary OR and presented at the strobe port. If no strobe signal is assigned to a strobe port,
the strobe port carries logic 0. For more detailed and timing information refer to Section 26.6.16, Strobe
Signal Support.
NOTE
In single channel device mode, channel B related strobe signals are
undefined and should not be assigned to the strobe ports.
Base + 0x0006 Write: Disabled Mode
0123456789101112131415
R
SMBA[15:4]
0000
W
Reset0000000000000000
Figure 26-5. System Memory Base Address Low Register (SYMBADLR)
Table 26-10. SYMBADR Field Descriptions
Field Description
SMBA System Memory Base Address — This is the value of the system memory base address for the individual
message buffers and sync frame table. This is the value of the system memory base address for the receive
FIFO if the FIFO address mode bit MCR[FAM] is set to 1. It is defines as a byte address.
Base + 0x0008 16-bit write access required Write: Anytime
0123456789101112131415
R0000
SEL
000
ENB
00
STBPSEL
WWMD
Reset0000000000000000
Figure 26-6. Strobe Signal Control Register (STBSCR)
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