Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-45
The driver (RxBD software producer) should set up some number of “empty” buffers for the Ethernet by
initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive
DMA) consumes these buffers by filling them with data as frames are received and clearing the E bit and
writing to the L (1 indicates last buffer in frame) bit, the frame status bits (if L = 1), and the length field.
If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the frame. For
non-last buffers, the length field in the receive BD is written by the DMA (at the same time the E bit is
cleared) with the default receive buffer length value. For end of frame buffers, the receive BD is written
with L = 1 and information written to the status bits (M, BC, MC, LG, NO, CR, OV, TR). Some of the
status bits are error indicators which, if set, indicate the receive frame should be discarded and not given
to higher layers. The frame status/length information is written into the receive FIFO following the end of
the frame (as a single 32-bit word) by the receive logic. The length field for the end of frame buffer is
written with the length of the entire frame, not just the length of the last buffer.
For simplicity the driver may assign the default receive buffer length to be large enough to contain an entire
frame, keeping in mind that a malfunction on the network or out of spec implementation could result in
giant frames. Frames of 2KB (2048) bytes or larger are truncated by the FEC at 2047 bytes so software is
guaranteed never to see a receive frame larger than 2047 bytes.
Similar to transmit, the FEC polls the receive descriptor ring after the driver sets up receive BDs and writes
to the RDAR register. As frames are received, the FEC fills receive buffers and updates the associated BDs,
then reads the next BD in the receive descriptor ring. If the FEC reads a receive BD and finds the E bit = 0,
it polls this BD once more. If the BD = 0 a second time, the FEC stops reading receive BDs until the driver
writes to RDAR.
25.5.2 Ethernet Receive Buffer Descriptor (RxBD)
In the RxBD, the user initializes the E and W bits in the first word and the pointer in second word. When
the buffer has been DMA’d, the Ethernet controller modifies the E, L, M, BC, MC, LG, NO, CR, OV, and
TR bits and writes the length of the used portion of the buffer in the first word. The M, BC, MC, LG, NO,
CR, OV and TR bits in the first word of the buffer descriptor are only modified by the Ethernet controller
when the L bit is set.
.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E RO1 W RO2 L — — M BC MC LG NO — CR OV TR
Offset + 2 Data Length
Offset + 4 Tx Data Buffer Pointer - A [0:15]
Offset + 6 Tx Data Buffer Pointer - A [16:31]
Figure 25-28. Receive Buffer Descriptor (RxBD)
To Next Page
Loading...
