NXP Semiconductors PXN2020 - 28.3.2.9 eMIOS200 Status Register (EMIOS_CSR[n])

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-19
28.3.2.9 eMIOS200 Status Register (EMIOS_CSR[n])
Offset: UC[n] base address + 0x0010 Access: User read/write
0 1234567891011121314 15
ROVR0000000000000 0 0
Ww1c
Reset0 0000000000000 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ROVFL000000000000UCINUCOUTFLAG
Ww1c
w1c
Reset0 0000000000000 0 0
Figure 28-11. eMIOS200 Status Register (EMIOS_CSR[n])
Table 28-12. EMIOS_CSR[n] Field Descriptions
Field Description
OVR Overrun Bit. The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set. This
bit can be cleared by clearing the FLAG bit or by software writing a 1.
0 Overrun has not occurred.
1 Overrun has occurred.
OVFL Overflow Bit. The OVFL bit indicates that an overflow has occurred in the internal counter. This bit must be
cleared by software writing a 1.
0 An overflow has not occurred.
1 An overflow has occurred.
UCIN Unified Channel Input Pin Bit. The UCIN bit reflects the input pin state after being filtered and synchronized.
UCOUT Unified Channel Output. The UCOUT bit reflects the output pin state.
FLAG FLAG Bit. The FLAG bit is set when an input capture or a match event in the comparators occurred. This bit
must be cleared by software writing a 1.
0 FLAG cleared.
1 FLAG set event has occurred.
Note: emios_flag_out reflects the FLAG bit value. When the DMA bit is set, the FLAG bit can be cleared by
the DMA controller.