NXP Semiconductors PXN2020 - 3.4.6.15 PF14 - GPIO (PF[14]); DSPI_D Data Input (SIN_D); 3.4.6.16 PF15 - GPIO (PF[15]); DSPI_D Peripheral Chip Select (PCS_D[0]); DSPI_A Peripheral Chip Select (PCS_A[5]); DSPI_B Peripheral Chip Select (PCS_B[4]); 3.4.7 Port G Pins; 3.4.7.1 PG0 - GPIO (PG[0]); DSPI_A Peripheral Chip Select (PCS_A[4]); DSPI_B Peripheral Chip Select (PCS_B[3]); Analog Input (AN[48])

Signal Description
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 3-31
3.4.6.15 PF14 — GPIO (PF[14]) / DSPI_D Data Input (SIN_D)
PF[14] is a GPIO pin. SIN_D is the data input pin for the DSPI D module.
3.4.6.16 PF15 — GPIO (PF[15]) / DSPI_D Peripheral Chip Select (PCS_D[0]) /
DSPI_A Peripheral Chip Select (PCS_A[5]) / DSPI_B Peripheral Chip
Select (PCS_B[4])
PF[15] is a GPIO pin. PCS_D[0] is a peripheral chip select input/output pin for the DSPI D module.
PCS_A[5] is a peripheral chip select output pin for the DSPI A module. PCS_B[4] is a peripheral chip
select output pin for the DSPI B module. PF[15] can be configured as a wakeup pin in the CRP_PWKENH
register.
3.4.7 Port G Pins
3.4.7.1 PG0 — GPIO (PG[0]) / DSPI_A Peripheral Chip Select (PCS_A[4]) /
DSPI_B Peripheral Chip Select (PCS_B[3]) / Analog Input (AN[48])
PG[0] is a GPIO pin. PCS_A[4] is a peripheral chip select output pin for the DSPI A module. PCS_B[3]
is a peripheral chip select output pin for the DSPI B module. AN[48] is a single-ended analog input pin.
3.4.7.2 PG1 — GPIO (PG[1]) / DSPI_A Peripheral Chip Select (PCS_A[5]) /
DSPI_B Peripheral Chip Select (PCS_B[4]) / Analog Input (AN[49])
PG[1] is a GPIO pin. PCS_A[5] is a peripheral chip select output pin for the DSPI A module. PCS_B[4]
is a peripheral chip select output pin for the DSPI B module. AN[49] is a single-ended analog input pin.
3.4.7.3 PG2 — GPIO (PG[2]) / DSPI_D Peripheral Chip Select (PCS_D[1]) / I
2
C_C
Serial Clock Line (SCL_C) / Analog Input (AN[50])
PG[2] is a GPIO pin. PCS_D[1] is a peripheral chip select output pin for the DSPI D module. SCL_C is
the serial clock signal for the I
2
C_C module. AN[50] is a single-ended analog input pin.
3.4.7.4 PG3 — GPIO (PG[3]) / DSPI_D Peripheral Chip Select (PCS_D[2]) / I
2
C_C
Serial Data Line (SDA_C) / Analog Input (AN[51])
PG[3] is a GPIO pin. PCS_D[2] is a peripheral chip select output pin for the DSPI D module. SDA_C is
the serial data line for the I
2
C_C module. AN[51] is a single-ended analog input pin.
3.4.7.5 PG4 — GPIO (PG[4]) / DSPI_D Peripheral Chip Select (PCS_D[3]) / I
2
C_B
Serial Clock Line (SCL_B) / Analog Input (AN[52])
PG[4] is a GPIO pin. PCS_D[3] is a peripheral chip select output pin for the DSPI D module. SCL_B is
the serial clock signal for the I
2
C_B module. AN[52] is a single-ended analog input pin.