Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-48 Freescale Semiconductor
Figure 31-41. DMA Controlled LIN RX Frame Generation and Reception
31.4.6.5 LIN Error Reporting
This section describes error checking and the signaling of detected errors in LIN mode.
31.4.6.5.1 Physical Bus Error Detection
If the receiver input is sampled 0 for at least 31 sample clock cycles after the start of the transmission of a
LIN frame, the physical bus error flag PBERR in the eSCI Interrupt Flag and Status Register 2
(eSCI_IFSR2) is set.
31.4.6.5.2 Unrequested Activity Detection
If an unrequested byte is received (i.e., a byte that is not part of an RX frame) that is not recognized as a
wakeup or break character, the bit error flag BERR in the eSCI Interrupt Flag and Status Register 2
(eSCI_IFSR2) is set. In addition, the RXRDY flag is set. The LINRX register must be read before normal
operations can proceed.
31.4.6.5.3 Standard Bit Error Detection
The standard bit error detection is performed on each byte field transmission.
During the transmission of the frame header and frame data, the receiver is running and receives the signal
values on the serial bus. After the complete transmission of a byte field, the eSCI compares the data that
was transmitted and the data that was received. If they do not match, the bit error flag BERR in the eSCI
Interrupt Flag and Status Register 2 (eSCI_IFSR2) is set.
31.4.6.5.4 Fast Bit Error Detection
Fast Bit Error Detection has been designed to allow flagging of LIN bit errors while they occur, rather than
flagging them after a byte transmission has completed (see Figure 31-42).
Figure 31-42. Fast Bit Error Detection on a LIN Bus
DMA
Controller
eSCI
CSM
TX DMA
channel
ID[5:0]P[1:0]
LEN
1
CSE CRC TD
2
TO[11:8]
DATA 1
DATA 2
DATA N
System Memory
1
LEN must be set to N
2
TD must be set to 0
Break Synch Identifier DATA 1 DATA N Checksum
LIN RX frame
TO[7:0]
RX DMA
channel
from LIN Master from LIN Slave
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