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NXP Semiconductors PXN2020 - Page 1037

NXP Semiconductors PXN2020
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Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-47
NOTE
When the eSCI module is in LIN mode and transmits the Header of an LIN
RX frame, if the CPU requests Stop Mode, the eSCI module may not
acknowledge the Stop Mode request and will stay in Normal Operating
Mode (not in lower power stop mode).
The application should ensure that no LIN transmission is running before it
requests Stop Mode by checking the Transmit Active and Receive Active
status bits in the eSCI Interrupt Flag and Status Register
(eSCI_IFSR1[TACT] and eSCI_IFSR1[RACT]).
31.4.6.4.2 DMA Controlled LIN RX Frames Generation
In this mode, the eSCI module controls the generation of LIN RX frame header and the reception of the
frame data automatically and utilizes the two connected DMA channels. Figure 31-40 provides a block
diagram that shows an overview of the DMA Controlled LIN RX Frame generation and reception. The
content of the header fields in the memory is the same as described in eSCI LIN Transmit Register
(eSCI_LTR) — LIN RX frame generation. The TX DMA channel is used the fetch the LIN RX frame
header and control information. The RX DMA channel is used to transfer the received frame data into the
memory.
When new data required for transmission, the module generates the transmit DMA request and the DMA
controller delivers the required data. When new data was received, the module generates the receive DMA
request and the DMA controller retrieves the provided data.
The application request the eSCI module to enter this mode by setting the RXDMA bit in the eSCI Control
Register 2 (eSCI_CR2). From this point in time, the module start the generation of DMA requests and
frame transmission and reception. Before entering this mode, the application should perform the following
actions:
1. Configure the module for LIN mode.
2. Enable transmitter and receiver by setting TE and RE in eSCI Control Register 1 (eSCI_CR1) to 1.
3. Set up the two DMA controller channels and provide frame header data in system memory.

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