Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-2 Freescale Semiconductor
Figure 25-1. FEC Block Diagram
25.1.2 Overview
The Ethernet media access controller (MAC) is designed to support both 10 and 100 Mbps Ethernet/IEEE
802.3 networks. An external transceiver interface and transceiver function are required to complete the
interface to the media. The FEC supports three different standard MAC-PHY (physical) interfaces for
connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10
Mbps-only 7-wire interface, which uses a subset of the MII signals.
The descriptor controller is a RISC-based controller that provides the following functions in the FEC:
Slave Interface
CSR
FIFO
DMA
Descriptor
Controller
MII
Receive
Tran smit
Bus
Controller
Controller
FEC_MDCFEC_MDIO
FEC_RX_CLK
FEC_RX_DV
FEC_RXD[3:0]
FEC_RX_ER
FEC_TX_CLKFEC_TX_EN
FEC_TXD[3:0]
FEC_TX_ER
FEC_CRS
MIB
(RISC +
microcode)
I/O
PAD
Counters
MII/7-WIRE DATA
OPTION
RAM
RAM I/F
FEC Bus
System Bus Crossbar Switch (XBAR)PBRIDGE_B
Master
FEC Block
MDO
MDEN
MDI
FEC_COL
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