System Clock Description
PXN20 Microcontroller Reference Manual, Rev. 1
5-6 Freescale Semiconductor
• Because the PXN20 uses a 16 MHz IRC as its default system clock, the FMPLL is put in PLL Off
mode during reset, so that power dissipation is minimized by disabling the FMPLL until needed
by the system.
• Programmable frequency multiplication factor settings generating VCO frequencies of
192 MHz – 600 MHz
• PLL Off mode (low-power mode)
• Register programmable output clock divider (ERFD)
• Programmable frequency modulation
— Modulation applied as a triangle waveform
— Peak-to-peak register programmable modulation depths of 0.5%, 1%, 1.5%, and 2% of the
system frequency
— Register programmable modulation rates of F
extal
/80, F
extal
/40, and F
extal
/20
• Lock detect circuitry provides a signal indicating the FMPLL has acquired lock and continuously
monitors the FMPLL output for any loss of lock
• Loss-of-clock circuitry monitors input reference and FMPLL output clocks with programmable
ability to select a backup clock source as well as generate a reset or interrupt in the event of a failure
• PLL Analog can be turned off if not used.
• The FMPLL cannot run in Sleep mode
5.2 System Clock Architecture
The PXN20 clocking architecture is shown in Figure 5-2. The figure shows all clock sources that are
available. It also shows clock selection and divider options that apply to each module. Peripheral sets are
shown in Table 5-1.
To optimize system power consumption, the PXN20 supports both system- and peripheral-level clock
dividers, and static clock gating using peripheral-level module disable (MDIS) bits and a system-level halt
mechanism. Figure 5-2 shows the device-level clock gating mechanism for the PXN20. These features are
detailed in Figure 5-3.
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