NXP Semiconductors PXN2020 - 28.8.4 Coherent Accesses

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-62 Freescale Semiconductor
Figure 28-60. Time Base Generation with Internal Clock and Clear on Match Start
Figure 28-61. Time Base Generation with Clear on Match End
28.8.4 Coherent Accesses
For IPWM and IPM modes, it is recommended that the software wait for a new FLAG set event before
reading EMIOS_CADR[n] and EMIOS_CBDR[n] registers to get a new measurement. The FLAG
indicates that new data has been captured and it is the only way to assure data coherency.
The FLAG set event can be detected by polling the FLAG bit or by enabling the interrupt or DMA request
generation.
Reading the EMIOS_CADR[n] register again in the same period of the last read of EMIOS_CBDR[n]
register may lead to incoherent results. This occurs if the last read of EMIOS_CBDR[n] register occurred
after a disabled B2 to B1 transfer.
System Clock
Prescaler Clock Enable
Internal Counter
Match Value = 3
0 13
0
2 0
3
0
PRESCALED CLOCK RATIO = 3
See Note
Note: When a match occurs, the first clock cycle is used to clear the internal counter,
1
2
FLAG Set Event
FLAG Clear
FLAG Pin/Register
and only after a second edge of prescaled clock the counter will start counting.
System Clock
Input Event/
Internal Counter
Match Value = 3
0 13
2 0
PRESCALED CLOCK RATIO = 3
See Note
Note: The match occurs only when the input event/prescaler clock enable is active.
Then, the internal counter is immediately cleared.
1
2
3
FLAG Set Event
FLAG Clear
FLAG Pin/Register
Prescaler Clock Enable