Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 6-19
6.3.3.2 Sleep Mode RAM Retention
The RAMSEL bits in the CRP_PSCR register determine the amount of RAM that remains powered in
sleep mode. This selection must be made prior to executing the WAIT instructions to the cores with the
CRP_PSCR[SLEEP] bit set.
6.3.4 Low-Power Operation
After the WAIT instructions have been executed with the SLEEP bit set, and the cores have cleanly halted,
the clock control block signals the CRP to enter the selected low-power mode.
At this point, the CRP has complete control of the device. Figure 6-15 shows the sequence to transition
from RUN mode to SLEEP. Figure 6-16 and Figure 6-17 give the transition diagram for going from RUN
mode to sleep, and then back to RUN mode.
The pads are put into a safe state during entry into Sleep mode. While is a safe state, the pad output buffers,
input buffers, and pull devices are disabled. The RESET pad retains its function. The input buffers for the
32 wakeup pins retain the same state as previous to Sleep mode entry. The TDO pin is still active if debug
is enabled before Sleep mode entry.
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