NXP Semiconductors PXN2020 - Page 154

Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
6-22 Freescale Semiconductor
Figure 6-17. SLEEP Mode Transition Diagram (Part 2)
13
- Device exits SLEEP
16
- Bias resistor off
- Negate system POR
Debug
Enabled?
- Block NPC debug
signals
- dbg clk = 16 MHz_IRC
- Assert core debug
enable
T
F
14
15
- Negate core debug
enable
- Set dbg clk = TCK
- TDO Pin Low
Mode Transition:
SLEEP
RUN
- Un-latch NPC
debug signals
- Negate TDO Pin
- Clear NPC PCR
Sleep Sync Bit
wait NPC PCR
sleep sync bit set
State 16
Figure 6-16
Go to INIT
(Figure 6-15)
wait core dbg ack