NXP Semiconductors PXN2020 - 25.3.4.24 Receive Buffer Size Register (EMRBR); 25.4 Functional Description

Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-29
25.3.4.24 Receive Buffer Size Register (EMRBR)
The EMRBR is a 32-bit register with one 7-bit field programmed by the user. The EMRBR register dictates
the maximum size of all receive buffers. Note that because receive frames are truncated at 2 KB – 1 bytes,
only bits 21–27 are used. This value should take into consideration that the receive CRC is always written
into the last receive buffer. To allow one maximum size frame per buffer, EMRBR must be set to
RCR[MAX_FL] or larger. The EMRBR must be evenly divisible by 16. To ensure this, bits 28-31 are
forced low. To minimize bus utilization (descriptor fetches) it is recommended that EMRBR be greater
than or equal to 256 bytes.
The EMRBR register does not reset, and must be initialized by the user.
25.4 Functional Description
This section describes the operation of the FEC, beginning with the hardware and software initialization
sequence, then the software (Ethernet driver) interface for transmitting and receiving frames.
Following the software initialization and operation sections are sections providing a detailed description
of the functions of the FEC.
Table 25-26. ETDSR Field Descriptions
Field Descriptions
X_DES_START Pointer to start of transmit buffer descriptor queue.
30–31 Reserved, should be cleared.
Offset: FEC_BASE + 0x0188 Access: User read/write
0123456789101112131415
R0 000000000000000
W
ResetUUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000
R_BUF_SIZE
0000
W
ResetUUUUUUUUUUUUUUUU
Figure 25-25. Receive Buffer Size Register (EMRBR)
Table 25-27. EMRBR Field Descriptions
Field Descriptions
0–20 Reserved, should be written to 0 by the host processor.
R_BUF_SIZE Receive buffer size.
28–31 Reserved, should be written to 0 by the host processor.