System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-3
— Power-on reset support
— Reset status register providing last reset source to software
— Software controlled reset assertion
• External interrupt
— 16 interrupt requests (139 inputs multiplexed down to 16 inputs in eight groups of 16 and one
group of 11, on Ports A through K)
— Rising or falling edge event detection
— Programmable digital filter for glitch rejection
•GPIO
— GPIO function on as many as 155 I/O pins
— Dedicated input and output registers for each GPIO pin.
— Parallel input and output registers with pins grouped into 16-bit ports (Ports A through K)
– Read/Write data is coherent with data written/read using dedicated input/output registers
• Internal multiplexing
— Allows flexible selection of ADC trigger inputs
— Allows selection of interrupt requests among external pins
— Allows selection of eMIOS inputs between external pins and deserialized DSPI outputs
— Allows selection of eMIOS outputs or SIU data register to be serialized via the DSPI
• System clock control
— Clock divider control for individual peripherals or peripheral groups for lower power operation
— Halt request registers to disable clocks to unused peripherals for lower power operation
— Halt acknowledge registers to determine when peripheral clocks are disabled
8.1.3 Modes of Operation
8.1.3.1 Normal Mode
In normal mode, the SIU provides the register interface and logic that controls system configuration, the
reset controller, GPIO, clock divider control, and peripheral clock disable/acknowledge.
8.1.3.2 Debug Mode
SIU operation in debug mode is identical to normal mode operation.
8.2 External Signal Description
Refer to Table 3-1 and Section 3.4, Detailed Signal Description, for signal properties.
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