Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-25
Since the frequency of the receiver clock is 16 times the frequency of the transmitter clock, each bit is
sampled 16 times. Each of the 16 samples of a bit has a sample number assigned, which is defined by the
receiver sample counter RSC. The nth sample is denoted by RSn. The receiver sample counter RSC is
updated with each rising edge of the receiver clock RCLK.
31.4.4 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated
bit time misalignment can cause one of the three stop bit data samples RS8, RS9, and RS10 to fall outside
the actual stop bit. A noise error occurs if the stop bit sample RS8, RS9, and RS10 samples are not all the
same logical value 1. A framing error occurs if the receiver clock is misaligned in such a way that the
majority of the RS8, RS9, and RS10 stop bit samples are a logic zero.
31.4.4.1 Faster Receiver Tolerance
In this case the receiver has a higher baud rate than the transmitter, thus the stop bit sampling starts already
in the last transmitted payload bit. To ensure the correct noise- and framing error-free reception of the stop
bit, the samples RS8, RS9, and RS10 must be located in the transmitted stop bit as shown in Figure 31-23.
Figure 31-23. Faster Receiver
The maximum tolerance that ensures error-free reception can be calculated with the assumption, that RS7
is sampled during the last transmitted payload bit and RS8 is sampled in the stop bit.
For an frame with n payload bits the transmitter starts the transmission of the stop bit
Eqn. 31-3
after the start of the transmission of the start bit.
For an frame with n payload bits, the receiver samples the RS8 sample of the stop bit
Eqn. 31-4
after the successful qualification of the start bit.
To ensure error-free reception of the stop bit, the transmitter must start the transmission of the stop bit
before the receiver samples RS8.
Eqn. 31-5
RCLK
START BIT
RXD
START BIT
QUALIFICATION
6 7 8 21 3
RSC
8 9 10
DATA
VOTING
PAYLOAD STOP BIT
6 7
rx
STOP
n1+=16RT
RE
7RT
RE
+
To Next Page
Loading...
