NXP Semiconductors PXN2020 - 32.1.2 DMA Interface

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
32-2 Freescale Semiconductor
Figure 32-1. I
2
C Block Diagram
32.1.2 DMA Interface
A simple DMA interface is implemented so that the I
2
C can request data transfers with minimal support
from the CPU. DMA mode is enabled by setting the DMAEN bit in the I
2
C Bus Control Register (IBCR).
DMA requests can be performed on all four I
2
C channels.
The DMA interface is only valid when the I
2
C module is configured for master mode and the DMA
channel mux has selected the I
2
C DMA request signals to be inputs to a DMA channel.
In/Out
Data
Shift
Register
Address
Compare
SDA
Interrupt
Clock
Control
Start
Stop
Arbitration
Control
SCL
Bus Clock
I
2
C
Registers