NXP Semiconductors PXN2020 - 26.5.2.55 Receive FIFO Depth and Size Register (RFDSR); 26.5.2.56 Receive FIFO A Read Index Register (RFARIR)

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-59
26.5.2.55 Receive FIFO Depth and Size Register (RFDSR)
This register defines the structure of the selected FIFO, i.e.,the number of entries and the size of each entry.
26.5.2.56 Receive FIFO A Read Index Register (RFARIR)
This register provides the message buffer header index of the next available FIFO A entry that the
application can read.
Table 26-64. RFSIR Field Descriptions
Field Description
SIDX
A
SIDX
B
Start Index — This field defines the number of the message buffer header field of the first message buffer of the
selected FIFO. The controller uses the value of the SIDX field to determine the physical location of the receiver
FIFO’s first message buffer header field.
Base + 0x008A Write: POC:config
0123456789101112131415
R
FIFO_DEPTH
A
/FIFO_DEPTH
B
0
ENTRY_SIZE
A
/ENTRY_SIZE
B
W
Reset0000000000000000
Figure 26-56. Receive FIFO Depth and Size Register (RFDSR)
Table 26-65. RFDSR Field Descriptions
Field Description
FIFO_DEPTH
A
FIFO_DEPTH
B
FIFO Depth — This field defines the depth of the selected FIFO, i.e.,the number of entries.
ENTRY_SIZE
A
ENTRY_SIZE
B
Entry Size — This field defines the size of the frame data sections for the selected FIFO in 2 byte entities.
Base + 0x008C
0123456789101112131415
R000000 RDIDX
W
Reset0000000000000000
Figure 26-57. Receive FIFO A Read Index Register (RFARIR)
Table 26-66. RFARIR Field Descriptions
Field Description
RDIDX Read Index — This field provides the message buffer header index of the next available FIFO message buffer
that the application can read.
If the old style FIFO mode is configured (MCR.FIMD = 0), the controller updates this index by 1 entry, when the
application writes to the FAFAIF flag in the Global Interrupt Flag and Enable Register (GIFER).
If the new style FIFO mode is configured (MCR.FIMD = 1), the controller updates this index by PCA entries,
when the application writes to the Receive FIFO Fill Level and POP Count Register (RFFLPCR).