Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-3
— Parameterized number of transfer attribute registers (from two to eight)
— Serial clock with programmable polarity and phase
— Various programmable delays
— Programmable serial frame size of 4 to 32 bits, expandable by software control
— Continuously held chip select capability
• Six peripheral chip selects, expandable to 32 with external demultiplexer
• Deglitching support for as many as 128 peripheral chip select with external demultiplexer
• DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
• Six Interrupt conditions:
— End of queue reached (EOQF)
— TX FIFO is not full (TFFF)
— Transfer of current frame complete (TCF)
— Attempt to transmit with an empty Transmit FIFO (TFUF)
— RX FIFO is not empty (RFDF)
— Frame received while Receive FIFO is full (RFOF)
• Modified SPI transfer formats for communication with slower peripheral devices
• Module disable mode supported via MDIS bits in the DSPI block
• Halt mode supported via HLT bits in the SIU block
The DSPI also supports pin reduction through serialization and deserialization.
• Two sources of serialized data:
— DSPI memory-mapped register
— Parallel Input signals
• Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register
• Transfer initiation conditions:
— Continuous
— Change in data
• Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
• Continuous serial communications clock
• Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the
Micro Second Bus downstream frame format.
30.1.3 DSPI Configurations
The DSPI block has three distinct serial transmission configurations; SPI, DSI and CSI.
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