Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
6-8 Freescale Semiconductor
6.2.2.3 RTC Status Register (CRP_RTSC)
The CRP_RTSC register contains:
• RTC interrupt flag
• API interrupt flag
• ROLLOVR Flag
CLKSEL Clock Select. The CLKSEL bits select the clock source for the RTC. CLKSEL should only be updated when
CNTEN is 0. The user should ensure that oscillator is enabled before selecting it as a clock source for RTC.
00 32 kHz OSC
01 128 kHz IRC
10 16 MHz IRC
11 4–40 MHz OSC
DIV512EN Divide by 512 enable. The DIV512EN bit enables the 512 clock divider. DIV512EN should only be updated
when CNTEN is 0.
0 Divide by 512 is disabled.
1 Divide by 512 is enabled
DIV32EN Divide by 32 enable. The DIV32EN bit enables the 32 clock divider. DIV32EN should only be updated when
CNTEN is 0.
0 Divide by 32is disabled.
1 Divide by 32 is enabled
APIVAL API Compare Value. The APIVAL bits are compared to an offset value based on bits 22–31 of the RTC counter.
If they match, a wakeup/interrupt request is asserted. APIVAL can be updated only when APIEN = 0 or when
the API function is undefined.
Note: API functionality starts only when APIVAL is non-zero. The first API interrupt takes two more cycles
because of synchronization of APIVAL to the RTC clock. After that, interrupts are periodic in nature. The
compare value is API + 1 and the minimum supported value is 4, because of synchronization issues.
Offset: CRP_BASE + 0x0014 Access: User read/write
0 1 234 5 6789101112131415
R 0 0 RTCF 0 0 0 0 0 0 0 0 0 0 0 0 0
W
w1c
Reset
1
0 0 000 0 0000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 APIF 0 0 ROVRF 0 0 0 0 0 0 0 0 0 0
W
w1c w1c
Reset
1
0 0 000 0 0000000000
1
These bits are only reset by power-on: VDD15 LVI, VDD33 LVI, and VDDSYN LVI, VDD5 low LVI, and VDD5 LVI.
Figure 6-4. RTC Status Register (CRP_RTSC)
Table 6-3. CRP_RTCC Field Descriptions (continued)
Field Description
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