Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 6-7
Offset: CRP_BASE + 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CNTE
N
RTCIE
FRZE
N
ROVREN
RTCVAL
W
Reset
1
0 0 0 0 0 0 0000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
APIEN APIIE CLKSEL DIV512EN DIV32EN APIVAL
W
Reset
1
0 0 0 0 0 0 0000000000
1
These bits are only reset by power-on: VDD15 LVI, VDD33 LVI, and VDDSYN LVI, VDD5 low LVI, and VDD5 LVI.
Figure 6-3. RTC Control Register (CRP_RTCC)
Table 6-3. CRP_RTCC Field Descriptions
Field Description
CNTEN Counter Enable. The CNTEN bit enable the RTC counter. Making CNTEN bit 1’b0 has the effect of
asynchronously resetting (synchronous reset negation) all the RTC and API logic. This allows for the RTC
configuration and clock source selection to be updated without causing synchronization issues.
0 Counter disabled.
1 Counter enabled.
RTCIE RTC Interrupt Enable. The RTCIE bit enables interrupts requests to the system if RTCF is asserted.
0 RTC interrupts disabled.
1 RTC interrupts enabled.
FRZEN Freeze Enable Bit. The counter freezes on entering the debug mode (as the ipg_debug is detected active) on
the last valid count value if the FRZEN bit is set. After coming out of the debug mode, the counter starts from
the frozen value.
0 Counter does not freeze in debug mode.
1 Counter freezes in debug mode.
ROVREN Counter Roll Over Wakeup/Interrupt Enable. The ROVREN bit enables wakeup and interrupt requests when
the RTC has rolled over from 0xFFFF_FFFF to 0x0000_0000. The RTCIE bit must also be set in order to
generate an interrupt from a counter rollover.
0) RTC rollover wakeup/interrupt disabled
1) RTC rollover wakeup/interrupt enabled.
RTCVAL RTC Compare Value. The RTCVAL bits are compared to bits 21–10 of the RTC counter. If they match, RTCF
is set.
Note: RTCVAL must be non-zero for a match to occur.
APIEN Autonomous Periodic Interrupt Enable. The APIEN bit enables the autonomous periodic interrupt function.
0 API disabled.
1 API enabled.
APIIE API Interrupt Enable. The APIIE bit enables interrupts requests to the system if APIF is asserted.
1 API interrupts enabled.
0 API interrupts disabled.
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