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NXP Semiconductors PXN2020 - 26.5.2.5 System Memory Base Address Register (SYMBADR)

NXP Semiconductors PXN2020
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FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-15
26.5.2.5 System Memory Base Address Register (SYMBADR)
CLKSEL Protocol Engine Clock Source Select — This bit is used to select the clock source for the protocol engine.
0 PE clock source is generated by on-chip crystal oscillator.
1 PE clock source is generated by on-chip PLL.
BITRATE FlexRay Bus Bit Rate — This bit field defines the FlexRay Bus Bit Rate.00010.0 Mbit/sec
000 10.0 Mbit/sec
001 5.0 Mbit/sec
010 2.5 Mbit/sec
011 8.0 Mbit/sec
100 reserved
101 reserved
110 reserved
111 reserved
Table 26-9. FlexRay Channel Selection
SCM CHB CHA Description
Dual Channel Device Modes
0
00
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN
not driven by controller
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN
not driven by controller
01
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN
driven by controller - connected to FlexRay channel A
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN
not driven by controller
10
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN
not driven by controller
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN
driven by controller - connected to FlexRay channel B
11
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN
driven by controller - connected to FlexRay channel A
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN
driven by controller - connected to FlexRay channel B
Single Channel Device Mode
1
00
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN
not driven by controller
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN
not driven by controller
01
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN
driven by controller - connected to FlexRay channel A
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN
not driven by controller
10
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN
driven by controller - connected to FlexRay channel B
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN
not driven by controller
11reserved
Base + 0x0004 Write: Disabled Mode
0123456789101112131415
R
SMBA[31:16]
W
Reset0000000000000000
Figure 26-4. System Memory Base Address High Register (SYMBADHR)
Table 26-8. MCR Field Descriptions
Field Description

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