Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 12-33
3. Write to any address in flash. This is referred to as an erase interlock write.
4. Write a logic 1 to the MCR[EHV] bit to start an internal erase sequence or skip to step 9 to
terminate.
5. Wait until the MCR[DONE] bit goes high.
6. Confirm MCR[PEG] = 1.
7. Write a logic 0 to the MCR[EHV] bit.
8. If more blocks are to be erased, return to step 2.
9. Write a logic 0 to the MCR[ERS] bit to terminate the erase.
The erase sequence is presented graphically in Figure 12-23. The erase suspend operation detailed in
Figure 12-23 is discussed in section Section 12.4.1.5, Flash Erase Suspend/Resume.
After setting MCR[ERS], one write (referred to as an interlock write) must be performed before
MCR[EHV] can be set to a 1. Data words written during erase sequence interlock writes are ignored. The
user may terminate the erase sequence by clearing MCR[ERS] before setting MCR[EHV].
An erase operation may be aborted by clearing MCR[EHV] assuming MCR[DONE] is low, MCR[EHV]
is high, and MCR[ESUS] is low. An erase abort forces the module to step 8 of the erase sequence. An
aborted erase results in MCR[PEG] being set low, indicating a failed operation. The blocks being operated
on before the abort contain indeterminate data. The user may not abort an erase sequence while in erase
suspend.
CAUTION
Aborting an erase operation leaves the flash core blocks being erased in an
indeterminate data state. This may be recovered by executing an erase on the
affected blocks.
12.4.1.5 Flash Erase Suspend/Resume
The erase sequence may be suspended to allow read access to the flash core. The erase sequence may also
be suspended to program (erase-suspended program) the flash core. A program started during erase
suspend can be suspended. One erase suspend and one program suspend are allowed at a time during an
operation. It is not possible to erase during an erase suspend, or program during a program suspend. During
suspend, all reads to flash core locations targeted for program and blocks targeted for erase return
indeterminate data. Programming locations in blocks targeted for erase during erase-suspended program
may result in corrupted data.
An erase suspend operation is initiated by setting the MCR[ESUS] bit. MCR[ESUS] can be set to a 1 at
any time when MCR[ERS] and MCR[EHV] are high and MCR[PGM] is low. A 0 to 1 transition of
MCR[ESUS] causes the flash module to start the sequence which places it in erase suspend. The user must
wait until MCR[DONE] = 1 before the module is suspended and further actions are attempted. After it is
suspended, the array may be read or a program sequence may be initiated (erase-suspended program).
Before initiating a program sequence the user must first clear MCR[EHV]. If a program sequence is
initiated, the value of the MCR[PEAS] is not reset. These values are fixed at the time of the first interlock
of the erase. Flash core reads from the blocks being erased while MCR[ESUS] = 1 return indeterminate
data.
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