NXP Semiconductors PXN2020 - 12.3.2.7 Address Register (ADR)

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-16 Freescale Semiconductor
12.3.2.7 Address Register (ADR)
The Address register (ADR) provides the first failing address in the event module failures (ECC or
PGM/Erase state machine)
The ADR register is shown in Figure 12-9 and Table 12-10.
Offset: FLASH_REGS_BASE + 0x0014 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000
HSEL
W
Reset0000000000000000
Figure 12-8. High Address Space Block Select Register (HBS)
Table 12-9. HBS Field Descriptions
Field Description
HSEL[5:0] High Address Space Block Select. High Address Block Select has the same characteristics as LSEL.
Offset: FLASH_REGS_BASE + 0x0018 Access: User read/write
0123456789101112131415
RSAD0000000000 ADDR
W
Reset0000000000000 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RADDR 000
W
Reset0000000000000 0 0 0
Figure 12-9. Address Register (ADR)