Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-36 Freescale Semiconductor
Table 36-24 details the status bit encodings.
36.6.8.4 Read/Write Access Address (RWA)
The read/write access address register provides the system bus address to be accessed when initiating a
read or a write access.
36.6.8.5 Read/Write Access Data (RWD)
The read/write access data register provides the data to/from system bus memory-mapped locations when
initiating a read or a write access.
MAP MAP Select.
000 Primary memory map.
001–111 Reserved.
PR Read/Write Access Priority.
00 Lowest access priority.
01 Reserved (default to lowest priority).
10 Reserved (default to lowest priority).
11 Highest access priority.
BST Burst Control.
0 Module accesses are single bus cycle at a time.
1 Module accesses are performed as burst operation.
CNT Access Control Count. Number of accesses of word size SZ.
ERR Read/Write Access Error. See Table 36-24.
DV Read/Write Access Data Valid. See Table 36-24.
Table 36-24. Read/Write Access Status Bit Encoding
Read Action Write Action ERR DV
Read access has not completed Write access completed without error 0 0
Read access error has occurred Write access error has occurred 1 0
Read access completed without error Write access has not completed 0 1
Not allowed Not allowed 1 1
Nexus Reg: 0x9 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Read/Write Address
W
Reset00000000000000000000000000000000
Figure 36-18. Read/Write Access Address Register (RWA)
Table 36-23. RWCS Field Description (continued)
Field Description
To Next Page
Loading...
